As the JK values are 1, the flip flop should toggle. Flip-flop stays in the state until the applied clock goes from 1 to 0. The timing diagram of the binary ripple counter clearly explains the operation.įrom the timing diagram, we can observe that Q0 changes state only during the negative edge of the applied clock. at the transition 1 to 0 of the clock pulse. As we have applied a high voltage to all the JK inputs of flip-flops they are at the state 1, so they must toggle the state at the negative going end of the clock pulse. This condition is used in ripple flip flop. So, according to the Truth table, when both the inputs are 1 the next state will be the complement of the previous state. The functioning of the counter can be easily understood using the Truth Table of JK flip flop. Here the output Q0 is the LSB and the output Q1 is the MSB bit. From the figure, it can be observed that the output Q0 of the first flip flop is applied as a clock pulse to the second flip flop. The symbol for the clock pulse indicates a negative triggered clock pulse.

JK inputs of flip flops are supplied with high voltage signal maintaining them at a state 1. Here two JK flip flops J0K0 and J1K1 are used. The circuit arrangement of a binary ripple counter is as shown in the figure below. While choosing the type of flip-flop it should be remembered that Ripple counters can be designed only using those flip-flops which have a condition for toggling like in JK and T flip flops. As here n value is 2 we use 2 flip-flops. Let us look at the working of a 2-bit binary ripple counter to understand the concept.Ī binary counter can count up to 2-bit values. Based on the number of flip flops used there are 2-bit, 3-bit, 4-bit…. The working of the ripple counter can be best understood with the help of an example. Ripple Counter Circuit Diagram and Timing Diagram

Jk flip flop multisim